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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jiang-Yi Shi Ai-Nv An Kang Li Yue Hao Pei-Yan Liu Ying Kang |
| Copyright Year | 2010 |
| Description | Author affiliation: School of Microelectronics, Xidian University, Xi'an 710071, China (Jiang-Yi Shi; Ai-Nv An; Kang Li; Yue Hao; Pei-Yan Liu; Ying Kang) |
| Abstract | This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A ‘ping-pong’ structure is adopted in SRAM interface logic which optimizes the memory data throughput. The test results show that the proposed architecture improves total performance by up to 64.1% compared with original memory controller and the 100% peak utilization of the data bus can be obtained. The efficiency of memory access shared by multi-processor cores is advanced remarkably. |
| Starting Page | 287 |
| Ending Page | 289 |
| File Size | 333121 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424457977 |
| e-ISBN | 9781424457984 |
| DOI | 10.1109/ICSICT.2010.5667755 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-01 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Delay Queueing analysis Optimization Decoding Bandwidth |
| Content Type | Text |
| Resource Type | Article |
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