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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yi-Chuen Eng Jyi-Tsong Lin |
| Copyright Year | 2010 |
| Description | Author affiliation: Dept. of EE, National Sun Yat-Sen Univ., Kaohsiung 80424, Taiwan, R.O.C. (Yi-Chuen Eng; Jyi-Tsong Lin) |
| Abstract | This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel effects significantly. More importantly, the single-crystal Si source/drain is achieved by the incorporation of the existing partially-insulating techniques into a NBO technology. The simulation results show that using the additional body regions which are the product of the ILP can help NBO MOSFETs achieve the ITRS roadmap requirements for high-performance applications. |
| Starting Page | 914 |
| Ending Page | 916 |
| File Size | 1092141 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424457977 |
| e-ISBN | 9781424457984 |
| DOI | 10.1109/ICSICT.2010.5667476 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-01 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | MOSFETs Semiconductor process modeling Logic gates Silicon Structural engineering Fabrication Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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