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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chin-Long Wey Shin-Yo Lin Wei-Chien Tang Muh-Tien Shiue |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Central Univ., Jhongli (Chin-Long Wey; Shin-Yo Lin; Wei-Chien Tang; Muh-Tien Shiue) |
| Abstract | Low cost yet efficient FFT (Fast Fourier Transform) processors are greatly needed for real-time operation in many OFDM applications. Taking the advantages of both memory-based and pipelined FFT architectures, this paper presents simple radix-2 memory-based FFT (MBFFT) Processors with low hardware cost and high maximum operation frequency. Results show that the core area of the proposed MBFFT is 1.79 $mm^{2}$ with the maximum operation frequency of 205 MHz, or a process speed of 269 mus for N=8192 points (24 bits per word). This also implies a throughput of 730 Mb/s (Mbits per second). This paper also presents parallel MBFFT structures with two and four butterfly processing elements (PEs), respectively, to improve the latency while still keeping low hardware cost and high maximum operation frequency. |
| Starting Page | 783 |
| Ending Page | 787 |
| File Size | 1980343 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424413775 |
| DOI | 10.1109/ICECS.2007.4511108 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-11 |
| Publisher Place | Morocco |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs OFDM Delay Hardware Throughput Memory architecture Fast Fourier transforms Feedback Circuits Digital video broadcasting Orthogonal Frequency Division Multiplexing (OFDM) Fast Fourier Transform (FFT) memory-based FFT multi-path delay commutator (MDC) FFT single-path delay feedback (SDF) FFT |
| Content Type | Text |
| Resource Type | Article |
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