NDLI: FPGA implementation of Fast Fourier Transform

Content Provider	IEEE Xplore Digital Library
Author	Vanmathi, K. Sekar, K. Ramachandran, R.
Copyright Year	2014
Description	Author affiliation: Dept. of EEE, Hindusthan Coll. of Eng. & Technol., Coimbatore, India (Vanmathi, K.; Sekar, K.; Ramachandran, R.)
Abstract	The Fast Fourier Transform is one of the most widely used digital signal processing algorithms. It is used to compute the Discrete Fourier Transform and its inverse. As a result, these are widely used for many applications in engineering, science, and mathematics which include areas such as: communications, signal processing, instrumentation, biomedical engineering, numerical methods, sonics and acoustics, and applied mechanics. It is described as the most important numerical algorithm of our lifetime. The number of applications for this transform continues to grow. The Decimation-In-Time radix-2 FFT using butterflies is designed. The butterfly operation is faster. The outputs of the shorter transforms are reused to compute many outputs, thus the total computational cost becomes less. The 16 bit and 32 bit inputs are synthesized using Verilog. The logic utilization obtained from the design summary of 16 and 32 bit radix-2 DIT FFT can be compared. The utilization factor increases as the number of bits increases. The design is developed using hardware description language Verilog on Xilinx 14.2 xc3s500E. The spartan3-tyro plus is used as hardware to implement the complex FFT values.
Starting Page	1
Ending Page	5
File Size	2501918
Page Count	5
File Format	PDF
e-ISBN	9781479949823
DOI	10.1109/ICGCCEE.2014.6922467
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Field Programmable Gate Array (FPGA) OFDM Discrete Fourier transforms Fast Fourier Transform (FFT) Signal processing algorithms Hardware Decimation in Time (DIT) Hardware design languages Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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