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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiang Gao Fei Wang Sheng Liu |
| Copyright Year | 2013 |
| Description | Author affiliation: Div. of MOEMS, Huazhong Univ. of Sci. & Technol., Wuhan, China (Xiang Gao; Fei Wang; Sheng Liu) |
| Abstract | Flip-chip packaging on organic substrate has been used widely as a promising package technology for the next generation of electronic devices. However, due to its numerous interfaces (i.e. die/passivation, passivation/underfill, underfill/solder mask, and solder mask/circuit board), it is more susceptible to a variety of complexworking and testing environments, delamination can easily take place in some critical sites, which is one of the greatest threats to its reliability. In this paper, delamination initiation and propagation behaviors of horizontal and vertical chip/underfill interfaces under temperature cycling tests are analyzed respectively by using cohesive zone model (CZM). The results indicate that delamination will occur first along the horizontal interface between chip and underfill and even when it propagates about 0.13mm, delamination still have not taken place at vertical interface. What's more, variance of phase angle with testing time and crack length is investigated. It turns out that when the crack is short, shearing stress dominates the contribution to causing the interfacial delamination, however, when the crack becomes long, the peeling stress gradually turns to be in the same range or even higher than that of shearing stress. Compared with interfacial delamination in vertical direction, the horizontal one induces a bigger threat to the reliability of flip-chip package because once it propagates to the solder joints, the fatigue life of solder would be reduced rapidly. The effect of interfacial delamination on fatigue life of solders is also implemented in this paper. It is found that plastic strain has been more than doubled in one temperature cycle when interfacial delamination is induced. Fatigue life is estimated by using modified Coffin-Mansin equation. It is found that induced interfacial delamination can decrease the solder's life by about 93.5%. Furthermore, the imperfection of underfill layers and some voids in the corners of the solder joints caused by the contamination of the flux residues in the corners of the solder joints are also taken into account. And the incremental inelastic strain caused by the voids is compared with that induced by interfacial delamination. It is found that interfacial delamination can lead to much higher plastic strain, that is to say, compared with process-induced defects, delamination has a much greater impact on solder's fatigue life and the whole package's reliability. |
| Sponsorship | IEEE Compon., Packag. Manuf. Technol. Soc. |
| Starting Page | 954 |
| Ending Page | 958 |
| File Size | 600977 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479904983 |
| DOI | 10.1109/ICEPT.2013.6756618 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-08-11 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delamination Stress Fatigue Flip-chip devices Strain Soldering Reliability reliability Flip-chip interfacial delamination fatigue life |
| Content Type | Text |
| Resource Type | Article |
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