NDLI: Reliability challenges and design considerations for Wafer-Level packages

Content Provider	IEEE Xplore Digital Library
Author	Xuejun Fan Qiang Han
Copyright Year	2008
Description	Author affiliation: Dept. of Eng. Mech., South China Univ. of Technol., Guangzhou (Xuejun Fan; Qiang Han)
Abstract	Wafer-level packaging (WLP) is essentially a true chip-scale packaging (CSP) technology, since the resulting package is practically of the same size as the die. Furthermore, wafer-level packaging paves the way for true integration of wafer fab, packaging, test, and burn-in at wafer level, for the ultimate streamlining of the manufacturing process undergone by a device from silicon start to customer shipment. There are several WLP technology classifications. Redistribution layer and bump technology, the most widely-used WLP technology, extends the conventional wafer fab process with an additional step that deposits a multi-layer thin-film metal rerouting and interconnection system to each device on the wafer. In this paper, an overview of the state of art WLP packaging technologies will be presented. The emphasis will be given to the challenges in reliability and the solutions based on the design.
Starting Page	1
Ending Page	6
File Size	721780
Page Count	6
File Format	PDF
ISBN	9781424427390
DOI	10.1109/ICEPT.2008.4607130
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Polymers Packaging Metals Reliability Copper Semiconductor device reliability Silicon
Content Type	Text
Resource Type	Article

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