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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jiang Zhou |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Mech. Eng., Lamar Univ., Beaumont, TX (Jiang Zhou) |
| Abstract | The objective of this paper is to simulate a JEDEC test board dynamic response with the use of a simplified analytical model. A block-diagram based Matlab/Simulink model was also built to perform the parametric study. It is found that the desirable predominated mode and no-ringing dynamic response can not be achieved for the test board and input profile with current JEDEC standard. Time durations of the input acceleration plays an important role in the dynamic response. The system response can be designed by carefully choosing the acceleration time duration. It is very meaningful in the design of board level drop test in the electronic industries. With the time duration adjusting to 1.5 times of the system period for the standard JEDEC test board, no-ringing response occurs. A closed-form theoretical solution was obtained for half-sine acceleration pulse input. The analytical simulation was confirmed by the theoretical results. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 1610426 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424427390 |
| DOI | 10.1109/ICEPT.2008.4607035 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-07-28 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Acceleration Mathematical model Analytical models Damping Finite element methods Modal analysis Packaging |
| Content Type | Text |
| Resource Type | Article |
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