NDLI: Multi-clock SOC test schedule based on TWC&S

Content Provider	IEEE Xplore Digital Library
Author	Zhang Jinyi Jiang Yanhui Lin Feng Wang Jia Sun Yan
Copyright Year	2008
Description	Author affiliation: Key Lab. of Adv. Displays & Syst. Applic., Shanghai Univ., Shanghai (Zhang Jinyi)
Abstract	Both wrapper and TAM are important components in SOC test architecture, and wrapper scan chain optimization and TAM optimization are NP-hard problems. Addressing wrapper scan chain optimization or TAM optimization separately leads to SOC test time sub-optimal. This paper presents a TWC&S (TAM/wrapper co-optimization and scheduling) algorithm for multi-clock SOC after combining the advantages of wrapper scan chain optimization and TAM optimization, and it aims to decrease test time of multi-clock SOC extremely. To demonstrate the validity of the proposed algorithm, experiment is performed on the multi-clock SOC $MCDS_{2}.$ The results show that there exist inflexion of test time, and the optimal test time is 23.2% when the widths of test bus are 20 vs. the least one. The phenomenon, decreasing degree of test time decreases slowly with test bus widths increase, demonstrates that trade-off will be achieved properly among test time, test area and design complexity.
Starting Page	1
Ending Page	4
File Size	190308
Page Count	4
File Format	PDF
ISBN	9781424427390
DOI	10.1109/ICEPT.2008.4607019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic cores System-on-a-chip IP networks Optimization Clocks Schedules Complexity theory scheduling multi-clock SOC wrapper optimization TAM optimization co-optimization
Content Type	Text
Resource Type	Article

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