NDLI: High performance flip chip PBGA development

Content Provider	IEEE Xplore Digital Library
Author	Stone, B. Czarnowski, J.M. Guajardo, J.R.
Copyright Year	2001
Description	Author affiliation: Semicond. Products Sector, Motorola Inc., Austin, TX, USA (Stone, B.)
Abstract	Flip Chip PBGA has been identified as a high performance packaging solution to meet the growing need for products with increased electrical performance, greater I/O density, and high system reliability. The development of a FC-PBGA presents several challenges due primarily to its sensitivity to moisture and the CTE mismatch between the silicon die and organic substrate. Potential risks and failure modes are encountered at all phases of environmental stressing. Moisture sensitivity is an obstacle in maintaining interfacial adhesion between the die surface and the underfill that is required to buffer the CTE mismatch. This critical interface becomes stressed during Moisture Pre-Conditioning, potentially leading to delamination. Once the adhesion issue is resolved, the underfill material will solidly couple the die to the substrate. The coupling is critical to minimizing bump interconnect fatigue, however, it also results in bending that may cause die cracking during thermal cycling. Additionally, fatigue in the organic substrate may develop during extended thermal cycling leading to further failure modes. The focus of this paper will be the development of the package materials and mechanical design, which were addressed subsequent to the successful development of a robust assembly process. The paper will discuss the challenges identified and overcome during package development that resulted in the successful qualification and introduction of a high performance Flip Chip PBGA package. It will discuss modeling and empirical identification of the primary failure modes and present approaches for addressing them. Through material selection, package design, and compatibility of the assembly process these obstacles can be overcome, resulting in a package suitable for markets requiring high electrical performance, high pin counts, and high system reliability.
Sponsorship	Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE
Starting Page	997
Ending Page	1002
File Size	694636
Page Count	6
File Format	PDF
ISBN	0780370384
ISSN	05695503
DOI	10.1109/ECTC.2001.927931
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Packaging Moisture Reliability Adhesives Fatigue Silicon Maintenance Delamination Robustness
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Underfill delamination to chip sidewall in advanced flip chip packages

Adhesion issues in flip-chip on organic modules

On thermal stresses and reliability of a PBGA chip scale package

Interfacial Delamination Mechanisms During Soldering Reflow With Moisture Preconditioning

Mechanisms of die and underfill cracking in flip chip PBGA package

Evaluation of the Delamination in a Flip Chip Using Anisotropic Conductive Adhesive Films Under Moisture/Reflow Sensitivity Test

Methodology for screening high performance underfill materials

Parametric reliability analysis of no-underfill flip chip package

Correlation of material properties to reliability performance of anisotropic conductive adhesive flip chip packages

High performance flip chip PBGA development

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Underfill delamination to chip sidewall in advanced flip chip packages

Adhesion issues in flip-chip on organic modules

On thermal stresses and reliability of a PBGA chip scale package

Interfacial Delamination Mechanisms During Soldering Reflow With Moisture Preconditioning

Mechanisms of die and underfill cracking in flip chip PBGA package

Evaluation of the Delamination in a Flip Chip Using Anisotropic Conductive Adhesive Films Under Moisture/Reflow Sensitivity Test

Methodology for screening high performance underfill materials

Parametric reliability analysis of no-underfill flip chip package

Correlation of material properties to reliability performance of anisotropic conductive adhesive flip chip packages

High performance flip chip PBGA development