NDLI: Development of low cost, highly reliable CSP using gold-gold interconnection technology

Content Provider	IEEE Xplore Digital Library
Author	Isozaki, S. Kimura, T. Shimada, T. Nakajima, H.
Copyright Year	2001
Description	Author affiliation: Div. of Packaging & Testing Eng., NEC Corp., Sagamihara, Japan (Isozaki, S.)
Abstract	A low cost, highly reliable CSP (Chip Size Package) named T-G/sup 2/BGA (tape gold-gold gang bond BGA), has been developed for compact, and light memory devices' package. T-G/sup 2/BGA has a structure that connects a chip and an interposer using gold-gold interconnection technology, which uses thermo-compression flip chip bonding. We studied the ways to interconnect gold stud bumps on chip and gold plated pads on tape metallurgically and succeeded in realizing a highly reliable package. T-G/sup 2/BGA can realize fan-in type, real chip size, package, and fan-out type package. For the fan-out type, sidefill resin or support ring is formed on overhang tape for solder ball coplanarity. Using TEG (test element group) samples, we selected the most suitable materials and optimized flip chip bonding conditions. Consequently, 60 pin fan-in type package was fabricated under optimized conditions using selected materials and memory device, and good reliability test results were obtained. On the other hand, 60 pin fan-out type package was fabricated with optimized sidefill resin, which showed good solder ball coplanarity and solder joint reliability. The gold stud bumps and gold pads interconnection technology is considered to be low cost, highly reliable and more suitable for CSP.
Sponsorship	Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE
Starting Page	63
Ending Page	68
File Size	2091770
Page Count	6
File Format	PDF
ISBN	0780370384
ISSN	05695503
DOI	10.1109/ECTC.2001.927686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Gold Resins Bonding Flip chip Conducting materials Chip scale packaging Aluminum Impurities Materials testing
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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