NDLI: Low cost high-speed flip chip assembly processing

Content Provider	IEEE Xplore Digital Library
Author	Gutentag, C. Dudderar, T.D.
Copyright Year	2001
Description	Author affiliation: Tempo Electron., Sherman Oaks, CA, USA (Gutentag, C.)
Abstract	Flip chip technology offers opportunities for dramatic improvements in high volume consumer electronics products. Keys to unlock these opportunities lie in the development of enabling technologies to reduce cost of manufacture combined with reliability enhancements. A new process technology has been developed and demonstrated for high-speed assembly/placement of singulated bare die in the flip chip (direct chip attach) orientation. Throughputs approaching 25,000 die placements per hour may be realized, depending upon the assembly process and the equipment employed for pick and place. Extremely high repeatability of each die position at the pick point enables 'blind-pick' assembling, with a potential X-Y placement accuracy of /spl plusmn/25 microns and /spl plusmn/1 degree in rotation. Die are packed in a tape and reel format. Quantities of 100,000 or more small die can be contained on a single reel, thereby minimizing downtime for component replenishment. Die sizes from 200 microns to 10 millimeters per side can be handled and presented for pick and place assembly from a 'super-intelligent' bare die dispenser, which is readily adapted to existing fine pitch placement machines. The process features an open architecture to permit inspection and test at die level, after singulation. This paper contains a detailed description of the high-speed transfer process enabled by die carrier tape technology together with illustrations of specific system applications now installed and operating in volume production.
Sponsorship	Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE
Starting Page	188
Ending Page	192
File Size	499765
Page Count	5
File Format	PDF
ISBN	0780370384
ISSN	05695503
DOI	10.1109/ECTC.2001.927716
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Flip chip Assembly Consumer electronics Electronic equipment manufacture Throughput Inspection Testing Production systems Wiring
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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