NDLI: A novel approach for incorporating silica filler into no-flow underfill

Content Provider	IEEE Xplore Digital Library
Author	Zhuqing Zhang Jicun Lu Wong, C.P.
Copyright Year	2001
Description	Author affiliation: Sch. of Mater. Sci. & Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Zhuqing Zhang)
Abstract	No-flow underfill technology has been proven to have potential advantages over the conventional underfill technology. However, due to the filler entrapment between solder bump and contact pad on board, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly using no-flow underfill, and has limited its application to large chip assemblies. This paper presents a novel approach to incorporate silica filler into no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is filled with 65 wt% silica fillers. The total filler loading of the mixture is estimated to be around 55 wt% using Thermo-Gravimetric Analyzer (TGA). The material properties of each layer of underfills and the underfill mixtures are characterized using Differential Scanning Calorimeter (DCS), Thermo-Mechanical Analyzer (TMA), Dynamic Mechanical Analyzer (DMA), and stress rheometer. FB250 daisy-chained test chips are assembled on FR-4 boards using the novel approach. A 100% yield of solder interconnect is achieved with filled no-flow underfill for the first time. Wetting of the eutectic SnPb solder to contact pad on the board is confirmed by Scanning Electronic Microscopy (SEM) and optical microscopic observation. An US patent is filed for this invention. The failure in normal no-flow underfill. Assembly with silica filler is investigated. Other variations of this process are discussed.
Sponsorship	Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE
Starting Page	310
Ending Page	316
File Size	1669778
Page Count	7
File Format	PDF
ISBN	0780370384
ISSN	05695503
DOI	10.1109/ECTC.2001.927741
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon compounds Assembly Optical microscopy Scanning electron microscopy Thermal expansion Polymers Materials reliability Flip chip Material properties Distributed control
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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