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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ping Miao Yixin Chew Tie Wang Foo, L. |
| Copyright Year | 2001 |
| Description | Author affiliation: Questech Solutions Pte. Ltd., Singapore, Singapore (Ping Miao) |
| Abstract | This paper presents two flip-chip assembly processes that enable an underfill with higher filler loading to be incorporated into the package. The first process includes dispensing the underfill containing higher filler loading on substrate surface, followed by chip placement and solder reflow under thermal compression. Apart from this, the second approach is virtually the modification of standard reflowable underfill process. The underfill with higher filler loading was spin-coated onto a bumped wafer surface and then cured. Subsequently, the top portion of bumps was exposed by laser treatment prior to wafer dicing. The diced chips with low CTE coating on the surface already were assembled via standard reflowable underfill process that includes dispensing reflowable underfill, chip placement and solder reflow through reflow oven. |
| Sponsorship | Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE |
| Starting Page | 174 |
| Ending Page | 180 |
| File Size | 1180374 |
| Page Count | 7 |
| File Format | |
| ISBN | 0780370384 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2001.927714 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-05-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Assembly Curing Silicon compounds Packaging Testing Instruments Surface treatment Coatings Thermomechanical processes Wafer scale integration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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