NDLI: Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique

Content Provider	IEEE Xplore Digital Library
Author	Seong-Min Lee Jin-Hyuk Lee Se-Yong Oh Ho-Kyoon Chung
Copyright Year	1995
Description	Author affiliation: Memory Div., Samsung Electron. Co. Ltd., Suwon, South Korea (Seong-Min Lee; Jin-Hyuk Lee; Se-Yong Oh; Ho-Kyoon Chung)
Abstract	The reliability tests were performed for the qualification of the high density memory devices assembled in SOJ (small outline J-leaded) packages utilizing a LOC (lead on chip) die attach technique and it was shown that the functional failure associated with a passivation break took place during T/C (thermal cycling) tests. To give a great insight into the passivation cracking phenomenon, a mechanism related to it was established through stress simulation and it was shown that the double-sided adhesive tape used for the attachment of the leadframe to the chip surface plays a significant role in defining degree of the passivation damage. The effect of the adhesive tape on the passivation damage was experimentally verified. Based on the established mechanism it is also discussed how the physical properties or the dimension of the LOC packaging materials influence the thermomechanical stability of the memory device and a proper design rule is suggested for the improvement of LOC package reliability.
Starting Page	455
Ending Page	462
File Size	795797
Page Count	8
File Format	PDF
ISBN	0780327365
DOI	10.1109/ECTC.1995.515321
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Passivation Packaging Lab-on-a-chip Testing Performance evaluation Qualifications Assembly Microassembly Thermal stresses Surface cracks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fractographic analysis on the die surface crack of a LOC packaged DRAM

Copper trace cracking under die perimeter of BGA packages: a combined effect of mold and die attach materials

Molding challenges of LOC packages with large devices

High temperature die-attach effects on die stresses

Polyimide fatigue induced chip surface damage in DRAM's Lead-On-Chip (LOC) packages

Molding compounds for thin surface mount packages and large chip semiconductor devices

Low stress polymer die attach adhesive for plastic packages

Assembly challenges for low modulus die attach material for MEMS devices

Effect of adhesive surface chemistry and morphology on package cracking in tapeless lead-on-chip (LOC) packages

Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique

Similar Documents

Fractographic analysis on the die surface crack of a LOC packaged DRAM

Copper trace cracking under die perimeter of BGA packages: a combined effect of mold and die attach materials

Molding challenges of LOC packages with large devices

High temperature die-attach effects on die stresses

Polyimide fatigue induced chip surface damage in DRAM's Lead-On-Chip (LOC) packages

Molding compounds for thin surface mount packages and large chip semiconductor devices

Low stress polymer die attach adhesive for plastic packages

Assembly challenges for low modulus die attach material for MEMS devices

Effect of adhesive surface chemistry and morphology on package cracking in tapeless lead-on-chip (LOC) packages

Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique