NDLI: A low-cost metal ball grid array for flip chip die

Content Provider	IEEE Xplore Digital Library
Author	Wilson, J.W. Moore, S.P. Laine, E.H.
Copyright Year	1995
Description	Author affiliation: IBM Corp., Endicott, NY, USA (Wilson, J.W.; Moore, S.P.; Laine, E.H.)
Abstract	A low cost ball grid array package has been developed for use with flip chip die. The structural "back bone" of this chip carrier is a metal plate which serves as a built-in heat spreader and a floating ground plane as well as the principal structural member of the package. Thin film circuitry is employed to make the necessary connections between the die and the solder balls. The fine line circuitization enables escape of many I/O from the flip chip die and thus a high I/O package with only a single layer of circuitry. The circuit lines are separated from the metal plate by means of a thin polymer dielectric layer. The die is attached to the carrier with a conventional high temperature C4 attach process. The ball grid array is on a 1.27 mm pitch. The metal plate that serves as the structural member of this package provides a number of benefits. The coefficient of thermal expansion (CTE) of the metal plate is very close to the CTE of the circuit card. The size of the package is not limited, therefore, in order to prevent fatigue and fracture of solder balls. The metal plate is separated from the circuitry by only a thin layer of dielectric material. The plate thus serves as a very effective floating ground plane and thereby provides improved electrical performance. The plate also serves as an effective heat spreader, again because of the thin dielectric layer separating the metal plate from the circuitry, the die and the solder balls. If added thermal performance is desired, a heat sink is easily attached to the backside of the metal plate. The thin film circuitry employed in this package also provides a number of benefits. The die and the solder balls are connected by a single layer of circuitry. Since electrical vias are not required, low cost processing is possible. Circuitization of the thin film metal can produce extremely fine lines and spaces; more than 700 I/O can be handled in a single layer.
Starting Page	42
Ending Page	45
File Size	429213
Page Count	4
File Format	PDF
ISBN	0780327365
DOI	10.1109/ECTC.1995.514359
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Flip chip Thin film circuits Costs Dielectric thin films Polymers Temperature Thermal expansion Fatigue Dielectric materials
Content Type	Text
Resource Type	Article

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