NDLI: High I/O plastic ball grid array packages-AT&T Microelectronics experience

Content Provider	IEEE Xplore Digital Library
Author	Cohn, C. Richman, R.M. Saxena, L.S. Shih, M.T.
Copyright Year	1995
Description	Author affiliation: AT&T Bell Labs., Allentown, PA, USA (Cohn, C.; Richman, R.M.; Saxena, L.S.; Shih, M.T.)
Abstract	AT&T Microelectronics package requirements for complex high-performance 0.5 /spl mu/m ASIC devices are currently in the 225 to 640 I/O range, 60 to 150 MHz, and 2 to 10 watt power dissipation. These requirements can be met with the traditional multilayer Ceramic Pin Grid Array (CPGA) packages or the lower Cost Plastic Pin Grid Array (PPGA). However, the ceramic and plastic PGAs are unwieldy and expensive at high I/O counts. Furthermore, through-hole packages are undesirable for customers who have switched to complete surface mount assembly lines. The plastic ball grid array (BGA) is a solution for lower cost, high I/O, high performance, surface mount and small outline package requirements. Using our extensive experience with plastic PGAs, we have extended the BGA technology to meet higher I/O and performance requirements. During the past two years we designed, developed and fabricated 235-388 I/O, four layer BGA packages. A 1995 production ramp up is under way. For improved electrical performance, vias were positioned to minimize trace lengths. Thermal performance was enhanced by the placement of thermal vias under the chip and direct connections to the ground plane. We have pursued two parallel BGA manufacturing paths with two different technologies: (a) overmolded BGAs through subcontract assembly; (b) Cavity type, liquid epoxy encapsulated for in-house assembly capability. Both types of BGA structures meet AT&T- ME's device qualification requirements and can be used to ship product. We are currently developing high performance 560 and 640 BGAs in a cavity down configuration. The packages will have power and ground planes and the chip will be directly attached to a heat spreading Cu slug. We are planning to offer the high performance BGAs in the 1996 time frame.
Starting Page	10
Ending Page	20
File Size	857694
Page Count	11
File Format	PDF
ISBN	0780327365
DOI	10.1109/ECTC.1995.514355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Plastic packaging Microelectronics Assembly Ceramics Costs Application specific integrated circuits Power dissipation Nonhomogeneous media Production
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Ball Grid Array Ceramic Packages

Microwave and millimeter wave ball grid array (BGA) packages

The realities of ASIC packaging

Ball Grid Array (BGA): The New Standard For High I/O Surface Mount Packages

Development of fine pitch ball grid array

Innovative circuit board level routing designs for BGA packages

Evaluation of lead(Pb)-free ceramic ball grid array (CBGA): Wettability, microstructure and reliability

The optimal choice of high pin count ASIC packages

Thermal performance comparison of high pin count cavity-up enhanced plastic ball grid array (EPBGA) packages

High I/O plastic ball grid array packages-AT&T Microelectronics experience

Similar Documents

Ball Grid Array Ceramic Packages

Microwave and millimeter wave ball grid array (BGA) packages

The realities of ASIC packaging

Ball Grid Array (BGA): The New Standard For High I/O Surface Mount Packages

Development of fine pitch ball grid array

Innovative circuit board level routing designs for BGA packages

Evaluation of lead(Pb)-free ceramic ball grid array (CBGA): Wettability, microstructure and reliability

The optimal choice of high pin count ASIC packages

Thermal performance comparison of high pin count cavity-up enhanced plastic ball grid array (EPBGA) packages

High I/O plastic ball grid array packages-AT&T Microelectronics experience