NDLI: Development of GE's plastic thin-zero outline package (TZOP) technology

Content Provider	IEEE Xplore Digital Library
Author	Forman, G.A. Fillion, R.A. Kolc, R.F. Wojnarowski, R.J. Rose, J.W.
Copyright Year	1995
Description	Author affiliation: Corp. Res. & Dev., Gen. Electr. Co., Schenectady, NY, USA (Forman, G.A.; Fillion, R.A.; Kolc, R.F.; Wojnarowski, R.J.; Rose, J.W.)
Abstract	One of the major obstacles impeding the wide spread use of multichip technology in the commercial electronics industries is the procurement and yield of bare chips. This area includes the reluctance of IC manufactures to supply bare chips due to the lack of standards, the difficulties associated with testing bare chips and their lack of confidence in the abilities of the MCM fabricators to assemble bare chips into MCMs without damaging good parts. Another aspect of die procurement is that bare chips are not generally available in TAB or flip-chip solder bump configurations. A highly flexible multichip interconnect approach has been developed with un-matched performance advantages that will be applicable to a wide range of commercial applications. Quick turn prototyping is made easy with maskless processing, electronic data entry, and integrated CAD CAM environment from customers, to engineering, to procurement and to manufacturing. This technology provides the highest density electronic packaging with its edge to edge chip spacing, its top mounted component capability and its 3D stacking and substrate thinning options. The basic electronic interconnection technology involves: plastic encapsulated single or multichip modules; flexible, conformable multichip on flex assemblies; non-planar single or multichip modules molded into conformal surfaces; and ball grid array MCM assemblies. These interconnect structures will be applied to digital, RF, analog, power conversion and mixed mode circuits.
Starting Page	664
Ending Page	668
File Size	989785
Page Count	5
File Format	PDF
ISBN	0780327365
DOI	10.1109/ECTC.1995.515353
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Plastic packaging Electronics packaging Procurement Assembly Integrated circuit interconnections Computer aided manufacturing Components, packaging, and manufacturing technology Multichip modules Impedance Electronics industry
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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