NDLI: Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN

Content Provider	IEEE Xplore Digital Library
Author	Boley, James Chandra, Vikas Aitken, Robert Calhoun, Benton
Copyright Year	2013
Description	Author affiliation: ARM R&D, San Jose, USA (Chandra, Vikas; Aitken, Robert) \|\| Dept. of ECE, University of Virginia, Charlottesville, USA (Boley, James; Calhoun, Benton)
Abstract	Circuit reliability in the presence of variability is a major concern for SRAM designers. With the size of memory ever increasing, Monte Carlo simulations have become too time consuming for margining and yield evaluation. In addition, dynamic write-ability metrics have an advantage over static metrics because they take into account timing constraints. However, these metrics are much more expensive in terms of runtime. Statistical blockade is one method that reduces the number of simulations by filtering out non-tail samples, however the total number of simulations required still remains relatively large. In this paper, we present a method that uses sensitivity analysis to provide a total speedup of ∼112X compared with recursive statistical blockade with only a 3% average loss in accuracy. In addition, we show how this method can be used to calculate dynamic VMIN and to evaluate several write assist methods.
Starting Page	1819
Ending Page	1824
File Size	973724
Page Count	6
File Format	PDF
ISBN	9781467350716
ISSN	15301591
e-ISBN	9783981537000
DOI	10.7873/DATE.2013.364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-18
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Transistors Monte Carlo methods Sensitivity analysis Random access memory Mathematical model Analytical models
Content Type	Text
Resource Type	Article

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