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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pomeranz, Irith |
| Copyright Year | 2013 |
| Description | Author affiliation: School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A. (Pomeranz, Irith) |
| Abstract | The goal of fault diagnosis is to identify a set of candidate faults, or fault locations, that explain an observed faulty output response of a chip. In fault diagnosis procedures that are based on specific fault models, a scoring algorithm can be used for defining sets of candidate faults that include the faults with the highest scores. This paper shows that it is possible to capture the underlying concepts that make fault scoring effective through a graph, which is referred to as the dominance graph. With a test set T used for fault diagnosis, the graph represents the dominance relations between the equivalence classes obtained with respect to T. The observed response Robs of a chip-under-diagnosis is associated with an equivalence class Cobs, and Cobs is added to the dominance graph. A candidate fault set is defined based on the dominance relations that are added to the graph due to the addition of Cobs. Certain properties of these dominance relations point to the type of the defect present in the chip, and the most appropriate algorithm for defining a set of candidate faults based on it. |
| Starting Page | 1083 |
| Ending Page | 1088 |
| File Size | 472952 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467350716 |
| ISSN | 15301591 |
| e-ISBN | 9783981537000 |
| DOI | 10.7873/DATE.2013.228 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-18 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Circuit faults Computational modeling |
| Content Type | Text |
| Resource Type | Article |
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