NDLI: Capturing post-silicon variation by layout-aware path-delay testing

Content Provider	IEEE Xplore Digital Library
Author	Zhang, Xiaolin Ye, Jing Hu, Yu Li, Xiaowei
Copyright Year	2013
Description	Author affiliation: State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China (Zhang, Xiaolin; Ye, Jing; Hu, Yu; Li, Xiaowei)
Abstract	With aggressive device scaling, the impact of parameter variation is becoming more prominent, which results in the uncertainty of a chip's performance. Techniques that capture post-silicon variation by deploying on-chip monitors suffer from serious area overhead and low testing reliability, while techniques using non-invasion test are limited in small scale circuits. In this paper, a novel layout-aware post-silicon variation extraction method which is based on non-invasive path-delay test is proposed. The key technique of the proposed method is a novel layout-aware heuristic path selection algorithm which takes the spatial correlation and linear dependence between paths into consideration. Experimental results show that the proposed technique can obtain an accurate timing variation distribution with zero area overhead. Moreover, the test cost is much smaller than the existing non-invasion method.
Starting Page	288
Ending Page	291
File Size	298519
Page Count	4
File Format	PDF
ISBN	9781467350716
ISSN	15301591
e-ISBN	9783981537000
DOI	10.7873/DATE.2013.071
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-18
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Logic gates Delays Fitting Temperature measurement Testing Monitoring layout-aware variation extraction path selection path-delay testing
Content Type	Text
Resource Type	Article

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