NDLI: Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown

Content Provider	IEEE Xplore Digital Library
Author	Chandra, V. Aitken, R.
Copyright Year	2011
Description	Author affiliation: ARM R&D, San Jose, CA (Chandra, V.; Aitken, R.)
Abstract	Progressive gate oxide breakdown is emerging as one of the most important source of stability degradation in nanoscale SRAMs, especially at lower supply voltages. Low voltage operation of SRAM arrays is critical in reducing the power consumption of embedded microprocessors, thus necessitating the lowering of Vmin. However, the oxide breakdown undesirably increases Fmin due to increase in dynamic write failures and eventually static write failures as the supply voltage decreases. In this work, we describe an analytical model based on the Kohlrausch-William-Watts (KWW) function to predict the degradation in the WLcrit as the oxide breakdown increases. The KWW model also accurately predicts the efficacy of the word-line boosting and Vdd lowering write-assist techniques in reducing WLcrit. Simulation results from an industrial low-power 32nm SRAM show that model is accurate to within 1% of SPICE across range of supply voltages and severity of oxide breakdown with orders of improvement in runtime.
Starting Page	1
Ending Page	4
File Size	171554
Page Count	4
File Format	PDF
ISBN	9781612842080
ISSN	15301591
e-ISBN	9783981080186
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Electric breakdown Logic gates Mathematical model Random access memory Analytical models Stability analysis Voltage control
Content Type	Text
Resource Type	Article

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