NDLI: Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

Content Provider	IEEE Xplore Digital Library
Author	Hameed, Fazal Bauer, Lars Henkel, Jorg
Copyright Year	2013
Description	Author affiliation: Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany (Hameed, Fazal; Bauer, Lars; Henkel, Jorg)
Abstract	On-chip DRAM caches may alleviate the memory bandwidth problem in future multi-core architectures through reducing off-chip accesses via increased cache capacity. For memory intensive applications, recent research has demonstrated the benefits of introducing high capacity on-chip L4-DRAM as Last-Level-Cache between L3-SRAM and off-chip memory. These multi-core cache hierarchies attempt to exploit the latency benefits of L3-SRAM and capacity benefits of L4-DRAM caches. However, not taking into consideration the cache access patterns of complex applications can cause inter-core DRAM interference and inter-core cache contention. In this paper, we contest to re-architect existing cache hierarchies by proposing a hybrid cache architecture, where the Last-Level-Cache is a combination of SRAM and DRAM caches. We propose an adaptive DRAM placement policy in response to the diverse requirements of complex applications with different cache access behaviors. It reduces inter-core DRAM interference and inter-core cache contention in SRAM/DRAM-based hybrid cache architectures: increasing the harmonic mean instruction-per-cycle throughput by 23.3% (max. 56%) and 13.3% (max. 35.1%) compared to state-of-the-art.
Starting Page	77
Ending Page	82
File Size	465468
Page Count	6
File Format	PDF
ISBN	9781467350716
ISSN	15301591
e-ISBN	9783981537000
DOI	10.7873/DATE.2013.030
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-18
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Interference Arrays Radiation detectors System-on-chip Magnetic cores Phase change random access memory
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

Reducing latency in an SRAM/DRAM cache hierarchy via a novel Tag-Cache architecture

Wear-Resistant Hybrid Cache Architecture with Phase Change Memory

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache

An sram main memory model (1997).

CHOP: Integrating DRAM Caches for CMP Server Platforms

Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches

Power management of hybrid DRAM/PRAM-based main memory

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

Similar Documents

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores

Reducing latency in an SRAM/DRAM cache hierarchy via a novel Tag-Cache architecture

Wear-Resistant Hybrid Cache Architecture with Phase Change Memory

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache

An sram main memory model (1997).

CHOP: Integrating DRAM Caches for CMP Server Platforms

Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches

Power management of hybrid DRAM/PRAM-based main memory

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores