NDLI: Bounding SDRAM interference: Detailed analysis vs. latency-rate analysis

Content Provider	IEEE Xplore Digital Library
Author	Shah, Hardik Knoll, Alois Akesson, Benny
Copyright Year	2013
Description	Author affiliation: Fortiss GmbH, Germany (Shah, Hardik) \|\| Technical University Munich, Germany (Knoll, Alois) \|\| CISTER-ISEP Research Centre, Portugal (Akesson, Benny)
Abstract	The transition towards multi-processor systems with shared resources is challenging for real-time systems, since resource interference between concurrent applications must be bounded using timing analysis. There are two common approaches to this problem: 1) Detailed analysis that models the particular resource and arbiter cycle-accurately to achieve tight bounds. 2) Using temporal abstractions, such as latency-rate (LR) servers, to enable unified analysis for different resources and arbiters using well-known timing analysis frameworks. However, the use of abstraction typically implies reducing the tightness of analysis that may result in over-dimensioned systems, although this pessimism has not been properly investigated. This paper compares the two approaches in terms of worst-case execution time (WCET) of applications sharing an SDRAM memory under Credit-Controlled Static-Priority (CCSP) arbitration. The three main contributions are: 1) A detailed interference analysis of the SDRAM memory and CCSP arbiter. 2) Based on the detailed analysis, two optimizations are proposed to the LR analysis that increase the tightness of its interference bounds. 3) An experimental comparison of the two approaches that quantifies their impact on the WCET of applications from the CHStone benchmark.
Starting Page	308
Ending Page	313
File Size	712986
Page Count	6
File Format	PDF
ISBN	9781467350716
ISSN	15301591
e-ISBN	9783981537000
DOI	10.7873/DATE.2013.075
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-18
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Interference SDRAM Equations Servers Clocks Timing Optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Bounding SDRAM interference: detailed analysis vs. latency-rate analysis

Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis

An SDRAM controller for real-time systems

Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs

Low-latency SDRAM controller for shared memory in MPSoC

Design of DDR4 SDRAM controller

A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control

Architectures and modeling of predictable memory controllers for improved system integration

An innovative design of the DDR/DDR2 SDRAM compatible controller

Bounding SDRAM interference: Detailed analysis vs. latency-rate analysis

Similar Documents

Bounding SDRAM interference: detailed analysis vs. latency-rate analysis

Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis

An SDRAM controller for real-time systems

Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs

Low-latency SDRAM controller for shared memory in MPSoC

Design of DDR4 SDRAM controller

A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control

Architectures and modeling of predictable memory controllers for improved system integration

An innovative design of the DDR/DDR2 SDRAM compatible controller

Bounding SDRAM interference: Detailed analysis vs. latency-rate analysis