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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Koc, Fahrettin Bozdas, Kenan Karsli, Burak Ergin, Oguz |
| Copyright Year | 2013 |
| Description | Author affiliation: Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, TURKEY (Koc, Fahrettin; Bozdas, Kenan; Karsli, Burak; Ergin, Oguz) |
| Abstract | Register renaming is a widely used technique to remove false dependencies in contemporary superscalar microprocessors. A register alias table (RAT) is formed to hold current locations of the values that correspond to the architectural registers. Some recently designed processors take a copy of the rename table at each branch instruction, in order to recover its contents when a misspeculation occurs. In this paper first we investigate the RAT vulnerability against transient errors. Then we analyze the vulnerability of RAT checkpoints and propose two techniques for soft error detection and correction utilizing redundantly taken copies of the entries whose content is the same with the previous and/or next checkpoints. Simulation results of the spec 2006 benchmarks reveal that on the average RAT vulnerability is 25% and checkpoint vulnerability is 6%. Results also reveal that redundancy exists at sequential checkpoint copies and can be used for error detection and correction purposes. We propose techniques that exploit this redundancy and show that faults in 41% of all checkpoints and 44% of rolled-back checkpoints can be detected and errors in 33% of the rolled-back checkpoints can be corrected. Since we exploit the already available storage, proposed error detection and correction techniques can be implemented with minimal hardware overhead. |
| Starting Page | 1494 |
| Ending Page | 1497 |
| File Size | 1041547 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467350716 |
| ISSN | 15301591 |
| e-ISBN | 9783981537000 |
| DOI | 10.7873/DATE.2013.304 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-18 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Registers Arrays Benchmark testing Redundancy Random access memory Microprocessors Hardware Error Detection and Correction Register Rename Checkpoint RAT Vulnerability Soft Error |
| Content Type | Text |
| Resource Type | Article |
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