NDLI: SVR-NoC: A performance analysis tool for Network-on-Chips using learning-based support vector regression model

Content Provider	IEEE Xplore Digital Library
Author	Qian, Zhiliang Juan, Da-Cheng Bogdan, Paul Tsui, Chi-Ying Marculescu, Diana Marculescu, Radu
Copyright Year	2013
Description	Author affiliation: Electronic and Computer Enineering, Hong Kong University of Science and Technology, Hong Kong (Qian, Zhiliang; Tsui, Chi-Ying) \|\| Eletrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA (Juan, Da-Cheng; Bogdan, Paul; Marculescu, Diana; Marculescu, Radu)
Abstract	In this work, we propose SVR-NoC, a learning-based support vector regression (SVR) model for evaluating Network-on-Chip (NoC) latency performance. Different from the state-of-the-art NoC analytical model, which uses classical queuing theory to directly compute the average channel waiting time, the proposed SVR-NoC model performs NoC latency analysis based on learning the typical training data. More specifically, we develop a systematic machine-learning framework that uses the kernel-based support vector regression method to predict the channel average waiting time and the traffic flow latency. Experimental results show that SVR-NoC can predict the average packet latency accurately while achieving about 120X speed-up over simulation-based evaluation methods.
Starting Page	354
Ending Page	357
File Size	466419
Page Count	4
File Format	PDF
ISBN	9781467350716
ISSN	15301591
e-ISBN	9783981537000
DOI	10.7873/DATE.2013.083
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-18
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Analytical models Vectors Training Accuracy Training data Feature extraction Support vector machines performance model Network-on-Chip learning
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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