NDLI: TSV redundancy: Architecture and design issues in 3D IC

Content Provider	IEEE Xplore Digital Library
Author	Ang-Chih Hsieh TingTing Hwang Ming-Tung Chang Min-Hsiu Tsai Chih-Mou Tseng Li, H.-C.
Copyright Year	2010
Description	Author affiliation: Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 300 (Ang-Chih Hsieh; TingTing Hwang) \|\| Global Unichip Corporation, Hsinchu, Taiwan 300 (Ming-Tung Chang; Min-Hsiu Tsai; Chih-Mou Tseng; Li, H.-C.)
Abstract	3D technology provides many benefits including high density, high band-with, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV may cause a number of known-good-dies that are stacked together to be discarded. This can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost for ASICs is proposed in this paper. Design issues including recovery rate and timing problem are addressed. Based on probabilistic models, some interesting findings are reported. First, the probability that three or more TSVs are failed in a tier is less than 0.002%. Assumption of that there are at most two failed TSVs in a tier is sufficient to cover 99.998% of all possible faulty free and faulty cases. Next, with one redundant TSV allocated to one TSV block, limiting the number of TSVs in each TSV block to be no greater than 50 and 25 leads to 90% and 95% recovery rates when 2 failed TSVs are assumed. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV bonding to 99.99%. This can effectively reduce the cost of manufacturing 3D ICs.
Starting Page	166
Ending Page	171
File Size	200661
Page Count	6
File Format	PDF
ISBN	9781424470549
ISSN	15301591
e-ISBN	9783981080162
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-08
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Through-silicon vias Three-dimensional integrated circuits Costs Bonding Redundancy Silicon Fabrication Timing Failure analysis Manufacturing
Content Type	Text
Resource Type	Article

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