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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mintarno, E. Skaf, J. Rui Zheng Velamala, J. Yu Cao Boyd, S. Dutton, R.W. Mitra, S. |
| Copyright Year | 2010 |
| Description | Author affiliation: Arizona State University, USA (Rui Zheng; Velamala, J.; Yu Cao) || Stanford University, CA, USA (Mintarno, E.; Skaf, J.; Boyd, S.; Dutton, R.W.; Mitra, S.) |
| Abstract | We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduces dynamic cooling as one of the self-tuning parameters, in addition to supply voltage and clock frequency. Our optimized self-tuning satisfies performance constraints at all times and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. Our framework features three control policies: 1. Progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2. Progressive-on-state-aging (POSA), which estimates aging by tracking active/sleep mode, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; 3. Progressive-real-time-aging-assisted (PRTA), which estimates the actual amount of aging and initiates optimized control action. Simulation results on benchmark circuits, using aging models validated by 45nm CMOS stress measurements, demonstrate the practicality and effectiveness of our approach. We also analyze design constraints and derive system design guidelines to maximize self-tuning benefits. |
| Starting Page | 586 |
| Ending Page | 591 |
| File Size | 305804 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Aging Clocks Cooling Voltage Frequency Constraint optimization Time factors Circuit simulation Semiconductor device modeling Stress measurement |
| Content Type | Text |
| Resource Type | Article |
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