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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Schliecker, S. Negrean, M. Ernst, R. |
| Copyright Year | 2010 |
| Description | Author affiliation: Institute of Computer and Network Engineering, Technische Universität Braunschweig, D-38106, Germany (Schliecker, S.; Negrean, M.; Ernst, R.) |
| Abstract | Predicting timing behavior is key to reliable real-time system design and verification, but becomes increasingly difficult for current multiprocessor systems on chip. The integration of formerly separate functionality into a single multicore system introduces new inter-core timing dependencies, resulting from the common use of the now shared resources. In order to conservatively bound the delay due to the shared resource accesses, upper bounds on the potential amount of conflicting requests from other processors are required. This paper proposes a method that captures the request distances of multiple shared resource accesses by single tasks and also by multiple tasks that are dynamically scheduled on the same processor. Unlike previous work, we acknowledge the fact that on a single processor, tasks will not actually execute in parallel, but in alternation. This consideration leads to a more accurate load model. In a final step, the approach is extended to allow addressing also dynamic cache misses that do not occur at predefined times but surface dynamically during the execution of the tasks. |
| Starting Page | 759 |
| Ending Page | 764 |
| File Size | 337262 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Performance analysis Multiprocessing systems Timing Real time systems System analysis and design System-on-a-chip Multicore processing Delay Upper bound Processor scheduling |
| Content Type | Text |
| Resource Type | Article |
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