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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ghosh, P. Sen, A. |
| Copyright Year | 2010 |
| Description | Author affiliation: Computer Science and Engineering Program, School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, USA, 85287 (Ghosh, P.; Sen, A.) |
| Abstract | Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority. |
| Starting Page | 654 |
| Ending Page | 657 |
| File Size | 365039 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Voltage Energy consumption Cost function Power engineering and energy Minimization Very large scale integration Computer science Power engineering computing Informatics Systems engineering and theory |
| Content Type | Text |
| Resource Type | Article |
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