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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Li Wang Jingling Xue Xuejun Yang |
| Copyright Year | 2010 |
| Description | Author affiliation: National Laboratory for Parallel and Distributed Processing, School of Computer, NUDT, China (Li Wang; Xuejun Yang) || Programming Languages & Compilers Group, School of Computer Science and Engineering, UNSW, Australia (Jingling Xue) |
| Abstract | This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in the development of a new representation for an unrolled and software-pipelined stream-level loop using a set of reuse equations, resulting in simultaneous optimization of two performance objectives for the loop, reuse and concurrency, in a unified framework. We have implemented this work in the compiler developed for our 64-bit FT64 stream processor. Our experimental results obtained on FT64 and by simulation using nine representative stream applications demonstrate the effectiveness of the proposed approach. |
| Starting Page | 1112 |
| Ending Page | 1117 |
| File Size | 208753 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Processor scheduling Concurrent computing Streaming media Kernel Delay Equations Pipeline processing Laboratories Program processors Distributed processing |
| Content Type | Text |
| Resource Type | Article |
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