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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sin-Yu Chen Rung-Bin Lin Hui-Hsiang Tung Kuen-Wey Lin |
| Copyright Year | 2010 |
| Description | Author affiliation: Computer Science and Engineering line, Yuan Ze University, Chung-Li, Taiwan (Sin-Yu Chen; Rung-Bin Lin; Hui-Hsiang Tung; Kuen-Wey Lin) |
| Abstract | Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured ASICs for leakage power reduction. We present a power-gated via-configurable logic block (PGVCLB) and a power gated design flow mostly using existing standard cell design tools. We can configure PGVCLBs in a design to implement fine-grained power gating, coarse-grained/cluster-based power gating or even distributed sleep transistor network (DSTN). With fine-grained power gating, we can achieve 52% leakage reduction on average with only 8% area and 17% delay overheads when compared to the data obtained using a non-power-gated library. |
| Starting Page | 514 |
| Ending Page | 519 |
| File Size | 603774 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Application specific integrated circuits Sleep Costs Delay Power engineering and energy Voltage Field programmable gate arrays Logic design Libraries Logic arrays structured ASIC power-gating low power via-configurable |
| Content Type | Text |
| Resource Type | Article |
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