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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nassif, S.R. Mehta, N. Yu Cao |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Electrical Engineering, Arizona State University, Tempe, 85287, USA (Yu Cao) || Department of Computer Science, California Institute of Technology, Pasadena, 91125, USA (Mehta, N.) || Austin Research Laboratory, IBM Corporation, TX 78758, USA (Nassif, S.R.) |
| Abstract | Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults. This paper examines the issue of circuit resilience, then proposes and demonstrates a roadmap for evaluating fault rates starting at the 45nm and going down to the 12nm nodes. The complete infrastructure necessary to make these predictions is placed in the open source domain, with the hope that it will invigorate research in this area. |
| Starting Page | 1011 |
| Ending Page | 1016 |
| File Size | 1586597 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Resilience Pulse inverters Circuit faults Random access memory Circuit noise CMOS technology CMOS logic circuits Circuit topology Latches Transistors |
| Content Type | Text |
| Resource Type | Article |
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