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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Alpaslan, E. Dworak, J. Kruseman, B. Majhi, A.K. Heuvelman, W.M. van de Wiel, P. |
| Copyright Year | 2010 |
| Description | Author affiliation: NXP Semiconductors High Tech Campus, Eindhoven, The Netherlands (Kruseman, B.; Majhi, A.K.; Heuvelman, W.M.; van de Wiel, P.) || Division of Engineering, Brown University, Providence, USA (Alpaslan, E.; Dworak, J.) |
| Abstract | As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon, this paper studies the effect of dynamic IR-drop on the delay of a path. We propose a noise index model, NIM, which can be used to predict the mismatch between expected and real path delays. The noise index considers both the proximity of switching activity to the path and physical characteristics of the design. To evaluate the method, we performed silicon measurements on randomly selected paths from an industrial 65nm design and compared these with Spice simulations. We show that a very strong correlation exists between the noise index model and the deviations between simulations and silicon measurements. |
| Starting Page | 1373 |
| Ending Page | 1376 |
| File Size | 481888 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Delay estimation Silicon Timing Circuit noise Semiconductor device modeling Circuit simulation CMOS technology Predictive models Delay effects Performance evaluation Post-Silicon Measurement Timing Mismatch Path Delay Test Performance Test Power Supply Noise IR-Drop |
| Content Type | Text |
| Resource Type | Article |
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