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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Facchini, M. Marchal, P. Catthoor, F. Dehaene, W. |
| Copyright Year | 2010 |
| Description | Author affiliation: IMEC - Interuniversity MicroElectronics Center, Kapeldreef 75, B-3001 Heverlee, Belgium (Facchini, M.; Marchal, P.; Catthoor, F.) || ESAT-MICAS Katholieke University Leuven, Kasteelpark Aremberg 10, B-3001 Heverlee, Belgium (Dehaene, W.) |
| Abstract | In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency and dimensions of the mapped memory, leading to potential performance limitations. In this paper we propose a one-time configurable memory tier designed to minimize the performances overhead due to the commodity. Flexible configuration is enabled by smart memory macros and I/Os organization and a customizable redistribution layer routing . With respect to the dynamic re-configurability, the proposed design offers up to 40% faster access time, while saving more than 10% of energy per access. In addition production cost trade offs are analyzed. |
| Starting Page | 291 |
| Ending Page | 294 |
| File Size | 1391110 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Random access memory Costs Logic design Delay Manufacturing Microelectronics Routing Production HDTV Merging |
| Content Type | Text |
| Resource Type | Article |
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