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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Meng Tie Haiying Dong Tong Wang Xu Cheng |
| Copyright Year | 2010 |
| Description | Author affiliation: Micro Processor Research and Development Center, Peking University, Beijing, China (Meng Tie; Haiying Dong; Tong Wang; Xu Cheng) |
| Abstract | Dual-Vth technique is a mature and effective method for reducing leakage power consumption. Previously proposed algorithms assign logic gates with sufficient timing slack to high threshold voltage to reduce leakage power without impact on timing. Meanwhile, clock skew scheduling algorithms are always utilized to optimize period or timing slack. In order to further reduce subthreshold leakage power consumption, in this paper, we ingeniously combine dual voltage assignment technique with intended clock skew scheduling: First, a leakage weight based clock skew scheduling algorithm is proposed to enlarge the leakage power optimization potential. Then we employ a dual-threshold voltage assignment algorithm to minimize leakage power. The experimental results on ISCAS89 benchmark circuits show that, within only several seconds, the leakage power can be further reduced by as much as 41.30% and by 9.87% on average with this new approach, compared to using the traditional method without considering clock skews. Three timing optimized industrial circuit blocks, among which each has around one hundred thousand gates, have also been optimized. It is shown that an average leakage power reduction of 9.95% can be achieved within minutes compared with traditional techniques. |
| Starting Page | 520 |
| Ending Page | 525 |
| File Size | 296349 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424470549 |
| ISSN | 15301591 |
| e-ISBN | 9783981080162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-03-08 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Clocks Delay Timing Circuits Flip-flops Job shop scheduling Energy consumption Scheduling algorithm Voltage Processor scheduling clock skew low power leakage dual-threshold |
| Content Type | Text |
| Resource Type | Article |
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