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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Loucif, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Software Eng. Dept., ALHOSN Univ., Abu Dhabi, United Arab Emirates (Loucif, S.) |
| Abstract | Torus is gaining a great interest in on-chip networks, and to further reduce torus diameter, hierarchical-torus networks have been proposed, where a cluster of IPs are connected by a single router. This paper investigates the performance merits of clustering in the torus, and compares the performance of the hierarchical-torus to that of the torus. Our simulation results show that, although hierarchical-torus has lower network diameter than the tours, the latter provides better latency performance. Hierarchical-torus suffers from the high load of traffic distributed on fewer channels, compared to the torus, resulting in high message blocking delays. Hierarchical-torus manages to outperform the torus only under local traffic distribution or when the fraction of hot-spot traffic is very large. Also, our results show hierarchical-torus greatly improves its performance in terms of message latency under deterministic routing with a small number of virtual channels, a performance which is almost similar to that obtained when messages are adaptive routed. |
| Starting Page | 837 |
| Ending Page | 842 |
| File Size | 1040941 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467362399 |
| e-ISBN | 9780769549521 |
| DOI | 10.1109/WAINA.2013.13 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-03-25 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Networks-on-Chip Torus Telecommunication traffic latency locality Routing Topology routing hot-spot Network topology Traffic control hierarchical networks System-on-chip IP networks |
| Content Type | Text |
| Resource Type | Article |
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