NDLI: Variation Aware Design of Post-Silicon Tunable Clock Buffer

Content Provider	IEEE Xplore Digital Library
Author	Suresh, V.B. Burleson, W.P.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA (Suresh, V.B.; Burleson, W.P.)
Abstract	Process variation is a major limiting factor in designing high performance circuits in advanced CMOS technologies. Over optimizing data paths to provide adequate design margin is leading to increased area and power overhead. In this work, we present a variation aware design of Post-Silicon Tunable (PST) clock buffers to redistribute clock skew and mitigate impact of process variation on chip performance. Conventional PST buffers are designed for linear delay values. We estimate a set of non-linear delay intervals of PST buffer based on slack variation in each critical path. The configuration device sizes are mapped to the non-linear delay intervals using a set of equality conditions and solved using Linear Programming (LP). The variation aware device sizing provides many small delay intervals within one standard deviation of slack distribution and fewer large delay intervals to compensate for larger slack variations. This helps in optimal tuning of PST buffers to fix hold time, as well as better skew distribution to achieve maximum possible performance in a chip. The proposed PST buffer design technique was implemented for ISCAS'89 benchmark circuits. Non-linear delay PST buffers improve performance binning yield by more than 4%. They also provide optimum buffer circuits with an area reduction of 30% and leakage power reduction of 20%. The proposed technique can be implemented by designing dedicated buffers for each critical path or using a smaller set of pre-designed buffers with non-linear delay values.
Sponsorship	IEEE Comput. Soc.
Starting Page	1
Ending Page	6
File Size	258138
Page Count	6
File Format	PDF
e-ISBN	9781479937653
DOI	10.1109/ISVLSI.2014.95
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Clocks Tuning Standards Inverters Mathematical model Clock Buffer Post-Si Tuning Process Variation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in