NDLI: Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms

Content Provider	IEEE Xplore Digital Library
Author	Yu-Guang Chen Yiyu Shi Kuan-Yu Lai Geng Hui Shih-Chieh Chang
Copyright Year	2012
Description	Author affiliation: Department of ECE, Missouri University of Science and Technology, Rolla, MO 65409, US (Yiyu Shi; Geng Hui) \|\| Department of CS, National Tsing Hua University, Hsinchu, Taiwan (Yu-Guang Chen; Kuan-Yu Lai; Shih-Chieh Chang)
Abstract	Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. The current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. Towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design.
Starting Page	309
Ending Page	316
File Size	971217
Page Count	8
File Format	PDF
ISBN	9781450315739
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Registers Clocks Latches Algorithm design and analysis Flip-flops Transistors Synchronization retention register Low power power gating
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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