NDLI: On logic synthesis for timing speculation

Content Provider	IEEE Xplore Digital Library
Author	Yuxi Liu Rong Ye Feng Yuan Kumar, R. Qiang Xu
Copyright Year	2012
Description	Author affiliation: CUhk REliable Computing Laboratory (CURE) The Chinese University of Hong Kong, Shatin, N.T., Hong Kong (Yuxi Liu; Rong Ye; Feng Yuan; Qiang Xu) \|\| Dept. of ECE, University of Illinois at Urbana-Champaign, USA (Kumar, R.)
Abstract	By allowing the occurrence of infrequent timing errors and correcting them with rollback mechanisms, the so-called timing speculation (TS) technique can significantly improve circuit energy-efficiency and hence has become one of the most promising solutions to mitigate the ever-increasing variation effects in nanometer technologies. As timing error recovery incurs non-trivial performance/energy overhead, it is important to reshape the delay distribution of critical paths in timing-speculated circuits to minimize their timing error rates. Most existing TS optimization techniques achieve this objective with post-synthesis techniques such as gate sizing or body biasing. In this work, we propose to conduct logic synthesis for timing-speculated circuits from the ground up. Being able to manipulate circuit structures during logic optimization, the proposed solution is able to dramatically reduce circuit timing error rates and hence improve its throughput, as demonstrated with experimental results on various benchmark circuits.
Starting Page	591
Ending Page	596
File Size	2818774
Page Count	6
File Format	PDF
ISBN	9781450315739
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Optimization Logic gates Delay Throughput Error analysis Error probability
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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