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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Abinaya, A. Sivaranjani, S. |
| Copyright Year | 2015 |
| Description | Author affiliation: M.E VLSI DESIGN M Kumarasamy Coll. of Eng., Karur, India (Abinaya, A.) || ECE, M. Kumarasamy Coll. of Eng., Karur, India (Sivaranjani, S.) |
| Abstract | Power reduction plays a vital role in VLSI design. Multi-bit flip-flop is an efficient method for clock power reduction. This method is to eliminate the redundant inverters by merging some flip-flops into multi-bit flip-flops. This multi-bit flip-flops can share the drive strength, dynamic power, area of the inverter chain and can even save the clock network power and facilitate the skew control. Firstly flip-flops that can be merged are identified based on synchronous clock signal and then a combination table is built to define the possible combination of flip-flops and finally a hierarchical way is used to merge flip-flops. |
| Starting Page | 326 |
| Ending Page | 330 |
| File Size | 263353 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781479972258 |
| DOI | 10.1109/ECS.2015.7124917 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-02-26 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Power demand Latches Merging Multi-bit flip-flop Inverters Synchronization Redundant inverters Flip-flops Clocks |
| Content Type | Text |
| Resource Type | Article |
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