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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jin-Fa Lee Yang Shao Zhen Peng |
| Copyright Year | 2012 |
| Description | Author affiliation: The Ohio State University, ElectroScience Lab., ECE Dept., 1320 Kinnear Rd., Columbus, OH 43212 (Jin-Fa Lee; Yang Shao; Zhen Peng) |
| Abstract | Advances in interconnect technologies, such as the increase of the number of metal layers and 3-D stacking technique, have paved the way for higher functionality and superior performance while reducing size, power, and cost in today's integrated circuits and package products. With the increase of clock frequency and edge rates as well as the continuously downscaling of feature size and 3-D interconnect technologies in high-speed systems, signal integrity (SI) effects such as signal delay, reflection, attenuation, dispersion and crosstalk have become one of the dominant factors in current deep sub-micrometer CMOS technologies limiting overall performance of high-speed systems. |
| Starting Page | 499 |
| Ending Page | 499 |
| File Size | 306613 |
| Page Count | 1 |
| File Format | |
| ISBN | 9781450315739 |
| ISSN | 10923152 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-11-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Silicon Integrated circuit interconnections Metals Educational institutions Conductivity Couplings |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Software |
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