NDLI: An efficient algorithm for library-based cell-type selection in high-performance low-power designs

Content Provider	IEEE Xplore Digital Library
Author	Li Li Peng Kang Yinghai Lu Hai Zhou
Copyright Year	2012
Description	Author affiliation: Analog Mixed Signal Group, Synopsys Inc, USA (Yinghai Lu) \|\| Electrical Engineering and Computer Science, Northwestern University, USA (Li Li; Peng Kang; Hai Zhou)
Abstract	In this paper, we present a complete framework for celltype selection in modern high-performance low-power designs with library-based timing model. Our framework can be divided into three stages. First, the best design performance with all possible cell-types is achieved by a Minimum Clock Period Lagrangian Relaxation (Min-Clock LR) method, which extends the traditional LR approach to conquer the difficulties in discrete scenario. Min-Clock LR fully leverages the prevalent many-core systems as the main body of its workload is composed of independent tasks. Upon a timing-valid design, we solve the timing-constrained power optimization problem by min-cost network flow. Especially, we identify and address the core issues in applying network flow technique to library-based timing model. Finally, a power prune technique is developed to take advantage of the residual slacks due to the conservative network flow construction. Experiments on ISPD 2012 benchmarks show that on average we can save 13% more leakage power on designs with fast timing constraints compared to start-of-the-art techniques. Moreover, our algorithm shows a linear empirical runtime, finishing the largest benchmark with one million cells in 1.5 hours.
Starting Page	226
Ending Page	232
File Size	552516
Page Count	7
File Format	PDF
ISBN	9781450315739
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Delay Logic gates Capacitance Optimization Solid modeling Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in