NDLI: Provably complete hardware Trojan detection using test point insertion

Content Provider	IEEE Xplore Digital Library
Author	Sheng Wei Kai Li Koushanfar, F. Potkonjak, M.
Copyright Year	2012
Description	Author affiliation: Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 (Kai Li; Koushanfar, F.) \|\| Computer Science Department, University of California, Los Angeles, Los Angeles, CA 90095 (Sheng Wei; Potkonjak, M.)
Abstract	This paper proposes a novel minimal test point insertion methodology that provisions a provably complete detection of hardware Trojans by noninvasive timing characterization. The objective of test point insertion is to break the reconvergent paths so that target routes for Trojan delay testing are specifically observed. We create a satisfiability-based input vector selection for sensitizing and characterizing each single timing path. Evaluations on benchmark circuits demonstrate that the test point-based Trojan detection can cover all circuit locations and can detect Trojans accurately with less than 5% performance overhead.
Starting Page	569
Ending Page	576
File Size	886840
Page Count	8
File Format	PDF
ISBN	9781450315739
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Logic gates Delay Trojan horses Vectors Equations Benchmark testing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Provably Complete Hardware Trojan Detection Using

Provably complete hardware trojan detection using test point insertion

Detection of hardware Trojan in SEA using path delay

Trojan Immune Circuits Using Duality

Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC

Malicious circuitry detection using fast timing characterization via test points

On timing-independent false path identification

Bi-decomposition of large Boolean functions using blocking edge graphs

Hardware security: Threat models and metrics

Provably complete hardware Trojan detection using test point insertion

Similar Documents

Provably Complete Hardware Trojan Detection Using

Provably complete hardware trojan detection using test point insertion

Detection of hardware Trojan in SEA using path delay

Trojan Immune Circuits Using Duality

Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC

Malicious circuitry detection using fast timing characterization via test points

On timing-independent false path identification

Bi-decomposition of large Boolean functions using blocking edge graphs

Hardware security: Threat models and metrics

Provably complete hardware Trojan detection using test point insertion