NDLI: Event-driven neural integration and synchronicity in analog VLSI

Content Provider	IEEE Xplore Digital Library
Author	Yu, T. Jongkil Park Joshi, S. Maier, C. Cauwenberghs, G.
Copyright Year	2012
Description	Author affiliation: Dept. of Electr. & Comput. Eng., UC San Diego, La Jolla, CA, USA (Jongkil Park; Joshi, S.) \|\| Silicon Valley Labs. of Texas Instrum., Santa Clara, CA, USA (Yu, T.) \|\| Dept. of Bioeng., UC San Diego, San Diego, CA, USA (Maier, C.; Cauwenberghs, G.)
Abstract	Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.
Sponsorship	IEEE Eng. Medicine Biol. Soc.
Starting Page	775
Ending Page	778
File Size	1076157
Page Count	4
File Format	PDF
ISBN	9781424441198
ISSN	1557170X
e-ISBN	9781457717871
DOI	10.1109/EMBC.2012.6346046
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neurons Delay Biomembranes Computer architecture Very large scale integration Routing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Biomedical Engineering Health Informatics Computer Vision and Pattern Recognition

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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