NDLI: CMOS biosensor system for on-chip cell culture with read-out circuitry and microfluidic packaging

Content Provider	IEEE Xplore Digital Library
Author	Welch, D. Christen, J.B.
Copyright Year	2012
Description	Author affiliation: Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA (Christen, J.B.) \|\| Sch. of Biol. & Health Syst. Eng., Arizona State Univ., Tempe, AZ, USA (Welch, D.)
Abstract	A 1.5 mm × 3 mm CMOS chip with sensors for monitoring on-chip cell cultures has been designed. The chip is designed in a 0.5 μm CMOS process which has 3 metal layers and 2 poly layers and is a 5 volt process. The chip contains ion sensitive field effect transistors (ISFETs), as well as ISFETs with read-out circuitry, for monitoring the pH of solutions placed on top of the chip. Interdigitated electrode structures (IDESs) are made using the top metal of the process to be used for sensing cellular attachment and proliferation via impendence. IDES read-out circuits and IDES test structures are included. The chip also contains test amplifiers, bandgap reference test structures, and connections for post-processing. We designed the chip to accommodate packaging into an environment where it will be directly exposed to a cell culture environment. Specifically we designed the chip to have the incorporated sensors near the center of the chip allowing for connections made around the edge of the chip to be sealed off using an epoxy or similar material to prevent shorting. Preliminary electrical characterization results for our amplifier indicate a gain of 48 dB, a bandwidth of 1.65 kHz, and a common mode rejection ratio (CMRR) of 72 dB. We also present a packaging technique using a flexible pcb substrate.
Sponsorship	IEEE Eng. Medicine Biol. Soc.
Starting Page	4990
Ending Page	4993
File Size	567472
Page Count	4
File Format	PDF
ISBN	9781424441198
ISSN	1557170X
e-ISBN	9781457717871
DOI	10.1109/EMBC.2012.6347113
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS integrated circuits Monitoring Metals Capacitance Capacitive sensors Packaging
Content Type	Text
Resource Type	Article
Subject	Signal Processing Biomedical Engineering Health Informatics Computer Vision and Pattern Recognition

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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