NDLI: Analog low-power hardware implementation of a Laguerre-Volterra model of intracellular subthreshold neuronal activity

Content Provider	IEEE Xplore Digital Library
Author	Ghaderi, V.S. Roach, S. Dong Song Marmarelis, V.Z. Choma, J. Berger, T.W.
Copyright Year	2012
Description	Author affiliation: Dept. Neurosci., Univ. of Southern California, Los Angeles, CA, USA (Roach, S.) \|\| Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA (Ghaderi, V.S.; Choma, J.) \|\| Dept. of Biomed. Eng., Univ. of Southern California, Los Angeles, CA, USA (Dong Song; Marmarelis, V.Z.; Berger, T.W.)
Abstract	The right level of abstraction for a model mimicking a neural function is often difficult to determine. There are trade-offs between capturing biological complexities on one hand and the scalability and efficiency of the model on the other. In this work, we describe a nonlinear Laguerre-Volterra model of the synaptic temporal integration of input spikes to postsynaptic potentials. This model is then efficiently implemented using analog subthreshold circuits and can serve as a foundation for future large-scale hardware systems that can emulate multi-input multi-output (MIMO) spike transformations in populations of neurons. The normalized mean square error in estimating real data using the circuit implementation of this model is less than 15%. The model components are modular and its parameters are adjustable for modeling temporal integration by neurons in other brain regions. The total power consumption of this nonlinear Laguerre-Volterra system is less than 5nW.
Sponsorship	IEEE Eng. Medicine Biol. Soc.
Starting Page	767
Ending Page	770
File Size	705056
Page Count	4
File Format	PDF
ISBN	9781424441198
ISSN	1557170X
e-ISBN	9781457717871
DOI	10.1109/EMBC.2012.6346044
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Low pass filters Neurons Brain modeling Integrated circuit modeling Estimation Biological system modeling
Content Type	Text
Resource Type	Article
Subject	Signal Processing Biomedical Engineering Health Informatics Computer Vision and Pattern Recognition

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A subthreshold aVLSI implementation of the Izhikevich simple neuron model

A programmable analog subthreshold biomimetic model for bi-directional communication with the brain

An analog circuit implementation of a Huber-Braun cold receptor neuron model

Iono-neuromorphic implementation of spike-timing-dependent synaptic plasticity

Implementing spiking neuron model and spike-timing-dependent plasticity with generalized Laguerre-Volterra models

A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation

Laguerre-volterra identification of spike-timing-dependent plasticity from spiking activity: A simulation study

Sparse generalized Laguerre-Volterra model of neural population dynamics

Electrical Morris-Lecar neuron

Analog low-power hardware implementation of a Laguerre-Volterra model of intracellular subthreshold neuronal activity

Similar Documents

A subthreshold aVLSI implementation of the Izhikevich simple neuron model

A programmable analog subthreshold biomimetic model for bi-directional communication with the brain

An analog circuit implementation of a Huber-Braun cold receptor neuron model

Iono-neuromorphic implementation of spike-timing-dependent synaptic plasticity

Implementing spiking neuron model and spike-timing-dependent plasticity with generalized Laguerre-Volterra models

A multichannel integrated circuit for neural spike detection based on EC-PC threshold estimation

Laguerre-volterra identification of spike-timing-dependent plasticity from spiking activity: A simulation study

Sparse generalized Laguerre-Volterra model of neural population dynamics

Electrical Morris-Lecar neuron

Analog low-power hardware implementation of a Laguerre-Volterra model of intracellular subthreshold neuronal activity