NDLI: Low cost fcCSP based on cu pillar

Content Provider	IEEE Xplore Digital Library
Author	Appelt, B.K. Chung, H. Chienfan Chen Wang, R. Hung, M.
Copyright Year	2011
Description	Author affiliation: Nantze Export Zone, Kaohsiung, Taiwan (Chung, H.; Chienfan Chen; Wang, R.; Hung, M.) \|\| ASE Group Inc., 1255 E Arques Ave, Sunnyvale, CA 94085, USA (Appelt, B.K.)
Abstract	Flip chip (fc) packaging has been practiced for many years but mainly for high end computer and certain automotive devices. RoHS has driven the conversion from lead-based fc bumps to lead-free (Pb-free) bumps. Pb-free was adopted more readily in consumer and mobile applications than in high reliability applications. A few years back, Intel introduced copper pillars (CuP) as an alternative to high Pb bumps to minimize electro-migration which was found at high currents in high performance applications. CuP was used in conjunction with Pb-free solder thereby achieving compliance with RoHS while at the same time improving reliability with superior electro-migration and thermal performance. Now, mobile applications are adopting CuP but primarily for fine pitch applications. CuPs are invariant in height and diameter during reflow unlike solder bumps which were also termed controlled chip collapse connections (C4). C4s have the advantage of self-aligning during solder reflow i.e. placement accuracy does not have to be extremely precise. With the advent of high precision die bonders, die with CuPs and small solder caps can be placed sufficiently accurate to enable mass reflow connections. CuPs do enable other significant advantages which do enable significant cost reductions. The fixed diameter of the pillars provides a larger pillar to pillar spacing as compared solder bumps at the same pitch and stand-off. The larger spacing which avoids any shorting concerns also potentially allows additional traces between bumps/pillars, thereby increasing the routability. Or alternatively, wider traces/spaces can be employed in the substrate design which equates to simpler substrate processes albeit lower substrate costs. The higher stand-off facilitates mold-only underfill processing which is also a significant process simplification i.e. cost reduction. Of course CuPs also present new challenges due to the very high stiffness, especially when assembled to lowK or ELK dies. Finite Element Modeling (FEM) has provided successful guidelines to overcome the stress induced damage that had been observed initially. Here, the advantages of CuP based fcCSP packaging will be detailed with design rules for pillars and substrates to achieve cost reductions. Further, FEM results and design guides for die CuP bumping will be given and substantiated by stress test results. Finally, a roadmap for CuP-fcCSP will be presented.
Starting Page	236
Ending Page	239
File Size	851265
Page Count	4
File Format	PDF
ISBN	9781457719837
e-ISBN	9781457719820
e-ISBN	9781457719813
DOI	10.1109/EPTC.2011.6184423
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Copper Substrates Nickel Reliability Encapsulation Finite element methods Bonding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Experimental and numerical investigations on Cu/low-k interconnect reliability during copper pillar shear test

Fine pitch flip chip chip scale packaging

Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip

Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

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Dynamic finite element analysis on underlay microstructure of Cu/low-K wafer during bonding process

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Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip

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