NDLI: Fine pitch flip chip chip scale packaging

Content Provider	IEEE Xplore Digital Library
Author	Appelt, B.K. Chung, H. Chienfan Chen Wang, R.
Copyright Year	2011
Description	Author affiliation: ASE Group, 1255E Arques Ave, Sunnyvale, CA, USA (Appelt, B.K.) \|\| ASE Group, Nantze Export Zone, Kaohsiung, Taiwan (Chung, H.; Chienfan Chen; Wang, R.)
Abstract	Flip chip packaging used to be the domain of micro processors and ASICs. Application processors were next to adopt flip chip packaging in high volume. Both types of packaging were based on solder interconnects, initially PbSn eutectic solder on organic substrates and then later Pb-free solders. In order to solve electro migration issues, micro processors adopted Cu pillars. Flip chip packages are now also adopting Cu pillars but primarily as a fine pitch solution because pillars can be formed as slender columns which are maintain their initial shape during assembly unlike solder. The invariant shape of the Cu pillars brings a number of other benefits such as increased, effective spacing between pillars and invariant pillar height which enable simpler substrate design and molded underfill. Those benefits result ultimately in a lower cost flip chip chip scale package. Cu pillars are stiffer than solder, especially eutectic solder, and are a concern when assembly on ELK die. Finite element modeling is very effective in identifying solution spaces which lead to reliable Cu pillar based flip chip packages. Development efforts of Cu pillars, their assembly and modeling will be described here.
Starting Page	1
Ending Page	4
File Size	982542
Page Count	4
File Format	PDF
ISBN	9781467306942
e-ISBN	9780956808608
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-12
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	IMAPS
Subject Keyword	modeling assembly fcCSP Nickel Cu pillars Copper Bonding Qualifications
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in