NDLI: Integration challenges of Cu pillars with extreme wafer thinning for 3D stacking and packaging

Content Provider	IEEE Xplore Digital Library
Author	Buisson, T. Potoms, G. Phommahaxay, A. Verbinnen, G. Jaenen, P. La Manna, A. Travaly, Y. Beyne, E.
Copyright Year	2011
Description	Author affiliation: IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium (Buisson, T.; Potoms, G.; Phommahaxay, A.; Verbinnen, G.; Jaenen, P.; La Manna, A.; Travaly, Y.; Beyne, E.)
Abstract	In this paper, we report on the development of Cu pillars and their impact on the subsequent thinning process for 3D applications. As the Cu pillars have a height of tens of microns (typically between 50–100µm), controlling the total thickness variation (TTV) after wafer thinning is becoming even more challenging. The Cu pillars are processed after completion of the Back End of Line (BEOL) with a target thickness of 50µm for a diameter of 80µm and a pitch of 200µm. The key challenge for 3D integration is the control of the wafer TTV after back grinding in order to allow TSV reveal. After optimization of the temporary wafer bonding in presence of high topography induced by 50µm high Cu pillars, a TTV after thinning below 5µm is achieved, which is comparable to the TTV obtained after wafer thinning without topography.
Starting Page	25
Ending Page	28
File Size	1431472
Page Count	4
File Format	PDF
ISBN	9781457719837
e-ISBN	9781457719820
e-ISBN	9781457719813
DOI	10.1109/EPTC.2011.6184379
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Copper Silicon Three dimensional displays Surfaces Bonding Coatings Resists
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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