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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jiale Han Haibin Chen Fei Wong Leung, K. Shiu, I. Jingshen Wu |
| Copyright Year | 2011 |
| Description | Author affiliation: Center for Engineering Materials and Reliability (CEMAR), Department of Mechanical Engineering, HKUST, Hong Kong (Jiale Han; Haibin Chen; Jingshen Wu) || NXP Semiconductors Hong Kong Limited, Hong Kong (Fei Wong; Leung, K.; Shiu, I.) |
| Abstract | In order to maximize product throughput, an increasing number of electronic packages, such as Small Outline Transistor (SOT) package, are manufactured in a package array mold. Due to the complicated structure design of the package and mold cavity, wire sweep is becoming an increasingly severe problem. In this study, the numerical model which had been validated by experimental work was used for wire sweep analysis. Firstly, the leadframe structure was studied. Given the thin thickness of leadframe and the relative position to the bond wire loop, the leadframe structure has very limited influence on the wire sweep value. Besides, for fixed width and length of the die, the wire sweep behavior was simulated to examine the influence of the die height (thickness). The results show that the thinner the die, the smaller the wire sweep. Furthermore, the effect of cavity height on wire sweep value was also estimated. Based on the previous simulation and analyses, the ratio of the die height to that of the cavity was introduced as an index to optimize the flow pattern of epoxy molding compound (EMC) in order to find a guideline for package and cavity design to avoid the wire sweep issue. In addition, the influence of injection velocity and viscosity of EMC on wire sweep during transfer molding process were inspected and discussed according to the simulation results as well. It can be further concluded that the velocity plays the key role in resulting in the severe wire sweep in package array mold during transfer molding process. |
| Starting Page | 667 |
| Ending Page | 673 |
| File Size | 2152050 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781457719837 |
| e-ISBN | 9781457719820 |
| e-ISBN | 9781457719813 |
| DOI | 10.1109/EPTC.2011.6184502 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-07 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wires Cavity resonators Lead Logic gates Transfer molding Electromagnetic compatibility Arrays |
| Content Type | Text |
| Resource Type | Article |
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